`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/14 18:58:20
// Design Name: 
// Module Name: IF_ID
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module IF_ID(
    input   wire        rst,
    input   wire        clk,
    input   wire        pause,
    
    input   wire [31:0] i_inst,
    input   wire [31:0] i_inst_addr,
    
    output  wire [31:0] o_inst,
    output  wire [31:0] o_inst_addr
    );
    
    reg [31:0] t_inst;
    reg [31:0] t_inst_addr;
    
    assign o_inst = t_inst;
    assign o_inst_addr = t_inst_addr;
    
    always @(posedge clk) begin
        if (rst == 0) begin
            t_inst <= 0;
            t_inst_addr <= 0;
        end else begin
            if (pause == 0) begin
                t_inst <= i_inst;
                t_inst_addr <= i_inst_addr;
            end
        end
    end
endmodule
